1. Field of the Invention
The present invention relates to integrated circuits in general and particularly to BIST macro or sub-system for testing high performance circuits.
2. Prior Art
The use of on-chip macros or BIST to generate test patterns which test various types of faults associated with electrical circuits are well known in the prior art. The prior art on-chips macros for testing faults are based on different types of architecture. One of the prior art architectures to which the present invention relates is the Twisted Ring Counter (TRC) based BIST. In this architecture the input scan register that provides test patterns to a Device Under Test (DUT) is reconfigured into a twisted ring counter whose outputs are correlated with initial test patterns called “seeds” to generate the test patterns used to test circuits.
Perhaps the most desirable characteristics of this type of architecture is pattern efficiency which means minimum number of seeds to generate maximum number of test patterns. Stated another way the main objective of this architecture is to use a relatively low number of seeds to generate relatively large number of test patterns. A detailed description of this architecture and improvement thereto are set forth in an article, entitled: “On Using Twisted Ring Counters for Test Set Embedding in BIST” published in Journal of Electronic Testing: Theory and Applications, December, 2001.
Even though the implementation set forth in the above identified article is a significant improvement over other prior art techniques, there is a need to improve the disclosed techniques even further to meet the needs of high performance circuits. The current trend in circuit technology is to build denser high performance circuits. As the circuit becomes denser less space is available on chips to store test patterns or seeds to test these circuits. As a consequence it is believed the need for improvements over the techniques discussed in the article will even be greater to satisfy the demand of testing these denser high performance circuits.